The present invention relates to a nonvolatile semiconductor memory device (EEPROM). More particularly, the present invention relates to an electrically erasable and programmable read only memory (EEPROM) for storing multilevel data. EEPROMs have the characteristic of nonvolatility. In EEPROMs, data can be stored by injecting and eliminating charges into floating gates by using the tunnel effect of a gate oxide film. Two-value data can be stored in each memory cell. A memory cell storing two-value data is called a binary cell. A memory cell storing more than two-value data is called a multilevel memory cell or an MLC. A representative example of such an MLC is a four-level memory cell capable of storing data “00”, “01”, “10”, or “11”. A conventional general multilevel memory cell MLC includes a memory cell transistor having a control gate, a floating gate, a drain, and a source. An n-type well is formed in a p-type substrate. In this configuration, the floating gate is electrically isolated, so that the charge can be trapped in a trap layer. To be specific, in the case of storing four-level data “00” to “11” in the multilevel memory cell, five threshold voltages are needed. More specifically, “00”, “01”, and “11” correspond to −2.5 V or less, −0.5 V or more, and 1.5 V or more, respectively. When the multilevel memory cell is in the “10” state, a threshold voltage should be 1.5 V or more and −0.5 V or less. As described above, conventionally, five states are defined for the four-level memory cell. As shown in FIG. 2, when a read reference voltage Vref is applied to a control gate of the memory cell transistor, a current Icell of the memory cell transistor (more specifically, a current flowing between the source and the drain) can be detected and determined by a sense amplifier (not shown). Hereinafter, the detected current Icell is referred to as a “cell current.” FIG. 3 is a graph illustrating the distribution of threshold voltages of the multilevel memory cell, for example, the four-level memory cell. As shown in FIG. 3, the four-level memory cell can store data “00”, “01”, “10”, and “11” by corresponding threshold voltages VT1 to VT4. In other words, “00” to “11” correspond to an area enclosed by a dotted line in FIG. 3. More specifically, the four-level memory cell stores one-bit data using four threshold voltages VT1 to VT4 within a threshold voltage distribution of the memory cell. For example, as shown in FIG. 3, “00” is associated with threshold voltages VT1 and VT2, “01” with threshold voltages VT3 and VT4, “10” with threshold voltages VT1 and VT4, and “11” with threshold voltages VT2 and VT3. In this case, a threshold voltage distribution of the memory cell is a “rectangular distribution.” According to the distribution of threshold voltages, the current of the memory cell transistor depends on the threshold voltage. In detail, in an erased state, a program operation is performed for a memory cell having a threshold voltage lower than −3.5 V by applying a program voltage to the control gate of the memory cell and a ground voltage to the substrate of the memory cell. To be specific, a channel of the memory cell is turned on due to a high electric field at the drain. As a result, hot electrons are generated at the edge of the drain junction. The hot electrons are injected into the floating gate by the electric field between the control gate and the floating gate of the memory cell transistor. In a programmed state, a program voltage lower than the threshold voltage of the memory cell is applied to the control gate of the memory cell. Therefore, a high electric field is generated between the control gate and the substrate, and hot holes are generated at the edge of the drain junction. Since the hot holes are larger in size than the hot electrons, the floating gate of the memory cell is negatively charged by the hot holes. As a result, a threshold voltage of the memory cell increases. As shown in FIG. 3, according to the conventional multilevel memory cell, the memory cell stores four-value data “00” to “11” based on different threshold voltages VT1 to VT4. However, according to the general multilevel memory cell, it is difficult to implement stable data characteristics. For example, as a memory cell transistor for storing one-bit data has a characteristic as shown in FIG. 4, an interval between two threshold voltages is small. Therefore, when two memory cells having the threshold voltage characteristics deviate from each other in a negative direction are connected to each other in series, a negative voltage margin between the threshold voltages is reduced. When this happens, a negative interference phenomenon can occur, so that data cannot be correctly read. Therefore, although the interval between the threshold voltages can be increased by changing the structure of the memory cell or optimizing a read voltage, it is still difficult to use the multilevel memory cell having such characteristics. As a result, the multilevel memory cell having the above-described characteristics is rarely used. It is almost impossible to produce a perfect memory cell having stable characteristics without the negative interference phenomenon. However, the negative interference phenomenon becomes severe as the number of read operations performed in a predetermined interval increases. Therefore, according to the conventional multilevel memory cell, an increase in the read cycle time may result in a malfunction. A conventional nonvolatile semiconductor memory device stores data using threshold voltages. Therefore, when a data read operation is performed after a program operation, a channel potential of a selected memory cell transistor is very low, so that a read margin is decreased. To be specific, when the channel potential of the selected memory cell is very low, a read current of the selected memory cell is small, so that a state transition of a memory cell having a threshold voltage between first and second read voltages may not be detected. Therefore, the nonvolatile semiconductor memory device malfunctions. Therefore, according to a conventional multilevel memory cell, when multilevel data is read after a program operation, the channel potential of the selected memory cell is low, so that the read margin becomes small. As a result, a program-read operation cycle time for the multilevel memory cell becomes long. Therefore, in order to obtain data more rapidly, a separate data read operation may be required after every program operation. Therefore, there are problems in that time taken to store data is extended and that the data programming time is increased. It is necessary to more precisely control a program operation, so that a threshold voltage distribution of a memory cell is sharp. However, a conventional multilevel memory cell has a large threshold voltage distribution width, so that an accurate control of the program operation is difficult. When an interval between threshold voltages of a multilevel memory cell is wide, the multilevel memory cell can obtain only a low threshold voltage margin between threshold voltages for distinguishing between states. Therefore, there is a need for the multilevel memory cell having a narrow interval between threshold voltages. When a multilevel memory cell includes a memory cell and a reference memory cell, a reference voltage must be applied to the reference memory cell, so that the multilevel memory cell can correctly read data using the reference voltage. However, conventionally, the multilevel memory cell includes only one reference memory cell. Therefore, it is difficult to implement a high reference voltage for determining an accurate data. In addition, when data is read after a program operation,