The present invention relates to a method of producing a semiconductor device having a semiconductor film formed on an insulating substrate and electrodes formed on the front surface of the semiconductor film. Hitherto, in a field-effect transistor (FET), a back gate bias (e.g., ground potential) has been applied to the gate electrode. FIG. 7 is a sectional view of a conventional field-effect transistor, and FIG. 8 is a graph showing the gate voltage applied to the gate of the field-effect transistor of FIG. 7. Referring to FIGS. 7 and 8, an insulating substrate 1 made of an insulating material such as, e.g., monocrystalline silicon is provided. A semiconductor film 2 made of, e.g., silicon is formed on the insulating substrate 1 by epitaxial growth or the like, and a source region 3 and a drain region 4 are formed in a predetermined portion of the semiconductor film 2. A gate insulating film 5 is formed on the semiconductor film 2 so as to be located above the channel region, and a gate electrode 6 is formed on the gate insulating film 5. A voltage is applied to the gate electrode 6 to control the potential of the channel region so that the device can perform an operation. In FIG. 8, the vertical axis represents the gate voltage applied to the gate electrode 6, and the horizontal axis represents the drain current Id. In the conventional field-effect transistor, since the gate voltage is equal to the ground voltage, i.e., 0 V in practice. In a conventional field-effect transistor having the structure shown in FIGS. 7 and 8, since the back gate voltage is 0 V in practice, the threshold voltage of the device is almost equal to the impurity concentration of the channel region. In a conventional field-effect transistor having the structure shown in FIGS. 7 and 8, however, since the gate electrode 6 is formed on the insulating substrate 1, the back gate voltage of the gate electrode 6 is 0 V. For this reason, as shown in FIG. 7, in some cases a depletion layer (depletion layer 7) is formed below the gate electrode 6. For this reason, the electric field in the vicinity of the boundary between the channel region and the depletion layer 7 becomes great so that the carrier mobility of the carrier in the vicinity of the boundary between the channel region and the depletion layer 7 is lowered. In a conventional field-effect transistor having the structure shown in FIGS. 7 and 8, further, since a voltage is applied between the source region 3 and the drain region 4 to thereby control the potential of the channel region, a gate-to-source capacitance and a gate-to-drain capacitance are formed between the gate electrode 6 and the source region 3 and between the gate electrode 6 and the drain region 4, respectively. For this reason, it is difficult to set the capacitance values of these capacitances to values optimal for the application of the transistor. In a conventional field-effect transistor having the structure shown in FIGS. 7 and 8, further, it is necessary to form the source region 3 and the drain region 4 by performing ion implantation, etching or the like after the gate electrode 6 is formed. Hence, an additional lithographic step is needed to produce the field-effect transistor. For this reason, the manufacturing cost increases. In a field-effect transistor having the structure shown in FIGS. 7 and 8, further, since the gate electrode 6 is formed on the insulating substrate 1, the wiring resistance of the gate electrode 6 becomes great. For this reason, it is difficult to reduce the size of the transistor and to produce a transistor having a high withstand voltage. In the conventional field-effect transistor having the structure shown in FIGS. 7 and 8, further, since the gate electrode 6 is formed on the insulating substrate 1, the wiring resistance of the gate electrode 6 becomes great. For this reason, the input and output signals between the gate electrode 6 and the external electrode are delayed, making it difficult to obtain a fast transistor. In the conventional field-effect transistor having the structure shown in FIGS. 7 and 8, further, since the gate electrode 6 is formed on the insulating substrate 1, the dielectric strength between the gate electrode 6 and the drain region 4 is degraded. For this reason, a high voltage cannot be applied between the gate electrode 6 and the drain region 4. A first object of the present invention is to provide a semiconductor device having a semiconductor film formed on an insulating substrate and electrodes formed on the front surface of the semiconductor film, in which a depletion layer is not formed below the gate electrode, a gate-to-source capacitance and a gate-to-drain capacitance can be set to optimal values, and a manufacturing method thereof. A second object of the present invention is to provide a semiconductor device having a semiconductor film formed on an insulating substrate and electrodes formed on the front surface of the semiconductor film, in which the gate electrode has low wiring resistance, the input and output signals between the gate electrode and the external electrode are not delayed, a fast transistor can be produced, and a manufacturing method thereof. A third object of the present invention is to provide a semiconductor device having a semiconductor film formed on an insulating substrate and electrodes formed on the front surface of the semiconductor film, in which the dielectric strength between the gate electrode and the drain region can be set to a high value, and a manufacturing method thereof. A first aspect of the present invention is directed to a semiconductor device comprising: an insulating substrate; a semiconductor film formed on the insulating substrate; an electrode formed on a surface of the semiconductor film; and a gate electrode formed on the insulating substrate. A second aspect of the present invention is directed to a semiconductor device comprising: an insulating substrate; a semiconductor film formed on the insulating substrate; an electrode formed on a surface of the semiconductor film; a gate electrode formed on the insulating substrate and electrically connected to the electrode; and a source electrode and a drain electrode formed in the semiconductor film and connected to the electrode, respectively. A third aspect of the present invention is directed to a semiconductor device comprising: an insulating substrate; a semiconductor film formed on the insulating substrate; an electrode formed on a surface of the semiconductor film; a gate electrode formed on the insulating substrate and electrically connected to the electrode; and a source electrode and a drain electrode formed in the semiconductor film and connected to the electrode, respectively. A fourth aspect of the present invention is directed to a semiconductor device comprising: a semiconductor film formed on an insulating substrate; an electrode formed on a surface of the semiconductor film; and a gate electrode formed on the insulating substrate and electrically connected to the electrode. A fifth aspect of the present invention is directed to a semiconductor device comprising: a semiconductor film formed on an insulating substrate; an electrode formed on a surface of the semiconductor film; and a gate electrode formed on the insulating substrate and electrically connected to the electrode, the gate electrode being electrically connected to a front surface of the semiconductor film. A sixth aspect of the present invention is directed to a semiconductor device comprising: a semiconductor film formed on an insulating substrate; an electrode formed on a surface of the semiconductor film; and a gate electrode formed on the insulating substrate and electrically connected to the electrode, the gate electrode being electrically connected to a front surface of the semiconductor film, a gate-to-source capacitance of the semiconductor device being set to be larger than a gate-to-drain capacitance of the semiconductor device. A seventh aspect of the present invention is directed to a semiconductor device comprising: a semiconductor film formed on an