The present disclosure relates generally to semiconductor structures, and more particularly, to a semiconductor structure and method for improving the adhesion between a contact structure and a metal electrode. In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to both the design of the circuit elements and the process methodology for manufacturing integrated circuits, leading to the development of complex integrated circuits having one million or more individual circuit elements, such as transistors, that are combined to form what may be referred to as functional blocks. Typically, the functional blocks may be combined to form a central processing unit (CPU), a D-side chip, a power management circuit, such as a PMIC (power management integrated circuit), static RAM (random access memory) or any other digital circuit. As chip designers and manufacturers continue to improve the processes used to form these complex integrated circuits, a certain number of defects in the chip may result from the manufacturing process. These defects must be eliminated to make a good chip and to keep production costs within reasonable limits. Faulty chips are usually detected by electrically testing certain chip components, such as the individual transistors, after fabrication of the chip. Typically, the testing of the individual transistors is performed by applying one or more electrical currents or voltages to the transistors and analyzing the result of such testing using any of a variety of well known testing techniques. The results of the testing are typically stored in non-volatile memory elements, such as, for example, one or more fuses or anti-fuses included in the chip. After completing the testing of all of the transistors in the chip, the fuses or anti-fuses are blown (or set to a high impedance state) by irreversibly changing the resistance or logic value of the particular element. Thereafter, defective transistors can be addressed using well known repair techniques. Alternatively, if desired, defective portions of the circuitry may be re-designed or discarded and new portions of the circuitry may be substituted. As chip complexity continues to increase, with the number of functional blocks and circuit elements per chip increasing as a function of time, a testing process that measures every portion of the chip becomes increasingly more complicated and time consuming. Because of the complexities involved with testing increasingly complex integrated circuit chips, it has become desirable to perform testing in functional blocks before full testing of the entire chip. Ideally, testing is performed such that faulty functional blocks can be identified before the formation of the chip is completed. The present disclosure relates to semiconductor structures and a method for forming them. More particularly, the present disclosure relates to a semiconductor structure including a plurality of conductive contact structures having a thin layer of metal over the top surfaces of the contact structures. The present disclosure also relates to a method for forming such a semiconductor structure. The teachings disclosed herein are not intended to be limited to implementations that solve any or all of the disadvantages of specific embodiments. It is to be appreciated that like reference numerals will be used to identify like elements illustrated in one or more of the figures.