The present invention is directed to a multi-layer printed wiring board of the so-called multi-layer interconnection structure (interlayer via) type, which is used for mounting electronic components on one or both sides of the board by way of, for example, so-called SMD (Surface Mount Device) mounting or the flip-chip mounting process. The interlayer via printed wiring board of the present invention is capable of attaining a high density by arranging a plurality of via holes and connecting layers having a low inter-vial resistance. In conventional interlayer via printed wiring boards, inter-vial holes (via holes) and conductive layers are arranged alternately on an insulating substrate such that each via hole is surrounded by a corresponding conductive layer. Accordingly, the size of an electronic component capable of being mounted on the board is limited. The electrical connection between the via hole and the associated conductive layer is made by a plating method. As described above, in conventional multi-layer interconnection structure printed wiring boards, the size of the component mounted on the board is limited. Further, a plating process for forming a conductive layer must be performed to connect the via hole and the conductive layer in each wiring layer, which increases the manufacturing cost. In view of the above, the present invention has an object of providing an interlayer via printed wiring board, which is capable of manufacturing a multi-layer structure capable of easily mounting a variety of components thereon and thereby realizing the high density arrangement of components, and is capable of manufacturing at low cost and in a short time. In order to accomplish the above object, the interlayer via printed wiring board of the present invention comprises an insulating substrate; a circuit conductor for electrically connecting electronic components, which is formed on the insulating substrate; and a via conductor formed on the insulating substrate, wherein the circuit conductor is formed by alternately stacking a first conductive layer and a second conductive layer on the insulating substrate; and the first and second conductive layers are connected by the via conductor. The via conductor comprises an insulative base layer, which is formed on the insulating substrate; a primary conductor layer having a plurality of first conductor projections, which are formed on the base layer and electrically connect the first conductive layer and the second conductive layer to each other; and a secondary conductor layer having a plurality of second conductor projections, which are formed on the base layer and electrically connect the second conductive layer to the first conductive layer. The base layer preferably has a thickness within a range of 15 xcexcm to 50 xcexcm. The first conductor projections and the second conductor projections are preferably formed of solder, copper, nickel or an alloy thereof. Each of the first conductor projections is preferably connected to the base layer at a position inside a bottom plane of the first conductor projection in a horizontal direction; and each of the second conductor projections is connected to the base layer at a position outside a bottom plane of the second conductor projection in a horizontal direction. Each of the first conductor projections is preferably connected to the base layer at a position above a bottom plane of the first conductor projection in a vertical direction; and each of the second conductor projections is connected to the base layer at a position below a bottom plane of the second conductor projection in a vertical direction. The first conductor projections and the second conductor projections are each preferably provided with a pair of inclined surfaces which are inclined toward a bottom plane of the first conductor projection in a horizontal direction and the base layer in a vertical direction, respectively. The first conductor projections and the second conductor projections are each preferably provided with a projection which is projected toward a bottom plane of the first conductor projection in a vertical direction and the base layer in a horizontal direction. The base layer preferably has a projection having a base surface which faces to a bottom plane of the base layer, and the first conductor projections are provided on the base surface. Each of the first and second conductive layers preferably has a thickness within a range of 100 xcexcm to 400 xcexcm. The insulating substrate preferably has an adhesive layer on its one or both sides to which the circuit conductor is bonded. According to the present invention, it is possible to form a plurality of via holes, each of which is surrounded by a corresponding first conductive layer and a second conductive layer having a low resistance, in an insulating substrate, and form a circuit conductor such that a plurality of electronic components can be mounted thereon by way of flip-chip mounting or SMD mounting. As a result, it is possible to improve the space factor in the case of mounting electronic components and to realize a multi-layer structure. In the case where the via holes are filled with a conductive material, it is possible to connect the via hole and the circuit conductor in the same layer. Since an electrical connection between the via hole and the corresponding circuit conductor is made by plating, it is possible to form a fine-pitch circuit conductor, and therefore, it is possible to improve the mounting density. In the interlayer via printed wiring board of the present invention, it is preferable that the circuit conductor is connected to a ground plane by way of a low resistance conductive layer which is formed on the insulating substrate and is filled into the via hole. In the interlayer via printed wiring board of the present invention, it is preferable that the first and second conductive layers are connected to each other by a metal wire layer which is formed on the insulating substrate and is also filled into the via hole. In the interlayer via printed wiring board of the present invention, it is preferable that the first conductor projections and the second conductor projections