The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device which is improved in moisture resistance and which has an insulating film made from an insulating material with high etching selectivity and a method of manufacturing the same. In general, semiconductor devices have a multi-layered wiring structure in which insulating films are formed over a silicon substrate (a semiconductor substrate), and wiring layers are connected to each other by the interposition of the insulating films. In a semiconductor device having such a structure, a gate insulating film made from, e.g., silicon dioxide (SiO.sub.2) or silicon nitride (SiN.sub.x) is formed at the interface between the gate electrode formed from a polysilicon film and the channel region in the semiconductor substrate, so as to improve electrical insulation between the gate electrode and the channel region. FIGS. 1 to 3 show a conventional method of manufacturing a semiconductor device having such a structure. First, as shown in FIG. 1, a low concentration p-type impurity, for example, boron (B) is implanted into the channel region of a semiconductor substrate 101 made from, e.g., silicon, thereby forming a channel stopper region 102. Then, a silicon dioxide film 103 with a thickness of about 50 nm, which is formed by CVD (chemical vapor deposition) or sputtering, is formed on the entire surface of the resultant substrate, and a silicon nitride film 104 with a thickness of about 100 nm, which is formed by LPCVD (low pressure CVD) or plasma CVD, is formed on the surface of the silicon dioxide film 103 by an ordinary manner. Thereafter, the silicon nitride film 104 and the silicon dioxide film 103 are selectively etched by using a mask (not shown), thereby forming openings to the source region and drain region. Then, as shown in FIG. 2, the portions of the silicon nitride film 104 and the silicon dioxide film 103 exposed by the formation of the openings are subjected to thermal oxidation, thereby forming field oxide films 105 of about 300 nm thick. Thereafter, a conductive film 106 made from, e.g., polycrystalline silicon is formed over the entire surface, and a silicon nitride film 107 made from, e.g., silicon nitride is formed on the surface of the conductive film 106. Thereafter, as shown in FIG. 3, the silicon nitride film 107 and the conductive film 106 are selectively etched by using a mask (not shown), thereby forming a gate electrode 108 having a channel region 109. Then, by using the gate electrode 108 as a mask, ion implantation of an n-type impurity, for example, phosphorus (P), is carried out, thereby forming a source region 110 and a drain region 111. As a result, the p-type channel stopper region 102 is brought into contact with the source region 110 in self-alignment. Then, after an interlayer insulating film 112 is formed on the entire surface, the surface of the resultant substrate is subjected to chemical mechanical polishing (CMP), thereby forming a contact hole 113 reaching the source region 110. Thereafter, an aluminum (Al) wiring layer is formed on the surface of the interlayer insulating film 112, and the aluminum wiring layer is patterned into a predetermined shape, thereby obtaining a semiconductor device having the above structure. However, in the above-described conventional method of manufacturing a semiconductor device, a problem arises such that the formation of the gate electrode is insufficient. In this method, when an interlayer insulating film is deposited to cover the gate electrode, a step is formed in the boundary between the lower gate electrode and the interlayer insulating film, and therefore defects in film quality or breakdown of the insulating film tend to occur in the step portion. For example, when the upper layer of the interlayer insulating film contains an impurity such as water, the impurity tends to penetrate through the interlayer insulating film into the gate electrode. If the impurity penetrates into the gate electrode, the gate electrode is increased in electric resistance or degraded in breakdown voltage. In addition, a gate electrode, particularly, a gate electrode made from polycrystalline silicon is disadvantageous in that it cannot be patterned by etching for a short time in dry etching. This is because, when the polycrystalline silicon film is etched, Si is generated by the reaction between the film and etching gas such as fluorine contained in the etching gas. The Si is volatilized, so as to deposit SiOx on the sidewall of the resultant pattern. Since SiOx has a higher dielectric constant than the polycrystalline silicon film and an insulating film formed thereon, the leakage current increases. In order to prevent this, it is necessary to carry out overetching until the sidewall of the polycrystalline silicon film is exposed. In this case, however, the lower layer of the gate electrode cannot be removed at the same time. For this reason, the lower layer of the gate electrode may be etched, thereby degrading the electrical characteristics of the semiconductor device. Furthermore, in the conventional method, when a gate electrode is formed by etching a polycrystalline silicon film for a short time, the etching rate of the gate electrode is lower than that of the etching rate of the sidewall of the gate electrode, and therefore the gate electrode cannot be etched at a high speed. In order to prevent this, it is necessary to increase the thickness of the sidewall of the gate electrode. However, an increase in the thickness of the sidewall results in an increase in the distance between the gate electrode and the source region. For this reason, an increase in the parasitic capacitance is caused, thereby degrading the performance of the semiconductor device. In addition, the conventional method has a problem in that the yield of the semiconductor device deteriorates. This is because in dry etching of the gate electrode, when the underlying interlayer insulating film, for example, contains an impurity such as water, defects in film quality tend to occur. In this case, even if only one of the portions in the pattern of the gate electrode is defective, the gate electrode cannot be connected to an external terminal, so that the semiconductor device has to be discarded. In general, the formation of a polycrystalline silicon film in a reduced pressure CVD system has problems such as degradation in yield of film formation and degradation in stability of the system, and therefore it is difficult to apply this method to semiconductor devices having a large area.