The present invention relates to a laser beam processing method in which a laser beam is irradiated on an irradiation area on an object to process the object, and more particularly to a laser processing method and laser processing apparatus suitable for processing the semiconductor integrated circuit. Recently, in accordance with progress of integrated circuits, it is necessary to form a large number of minute patterns on the semiconductor integrated circuit. Also, in the field of the semiconductor integrated circuit, it is common that the device isolation process in which grooves are formed for isolation of elements and then an insulating film is formed on the device isolation grooves. In the device isolation process, as shown in FIGS. 1A to 1E, the groove for the element isolation is formed by first forming a pad oxide film 21 on a semiconductor substrate 20, then forming a silicon nitride film 22 as shown in FIG. 1A, then patterning and etching the silicon nitride film 22 by using a photoresist 23 as a mask, then removing the photoresist 23 as shown in FIG. 1B, then depositing a pad oxide film 24 on an entire surface of the resultant structure as shown in FIG. 1C, then forming a nitride film 25 on the pad oxide film 24, and then patterning the nitride film 25 by using the photoresist 26 as a mask as shown in FIG. 1D, then removing the photoresist 26 as shown in FIG. 1E. The above-mentioned patterning is executed by photolithography using a mask alignment mark 20A. Namely, an alignment mark 23A for patterning the photoresist 23, and an alignment mark 26A for patterning the photoresist 26 are formed on the pad oxide film 24 as shown in FIGS. 1B and 1E. In this case, a portion surrounded by the solid line 21A of the pad oxide film 21 may be used as the alignment mark 23A for patterning the photoresist 23, and a portion surrounded by the broken line 24A of the pad oxide film 24 may be used as the alignment mark 26A for patterning the photoresist 26. Accordingly, it is possible to form the grooves in the desired shape. In the above-mentioned prior art, as described above, the nitride film 22, which is a shading film for forming the alignment marks 23A and 26A, is deposited on the pad oxide film 21. However, it is necessary to deposit a large amount of the nitride film 22 because the alignment marks 23A and 26A are necessary. Accordingly, for example, when the groove width is 0.1 .mu.m, and the groove depth is 1 .mu.m, the thickness of the nitride film 22 becomes approximately 200 nm to 350 nm. In the etching process of the nitride film 25, which is a shading film for forming the alignment mark 26A, it is impossible to determine the alignment mark 26A in accordance with the mark 23A because the thickness of the pad oxide film 24 is 200 nm or more. Accordingly, the mask alignment of the photoresist 26 becomes difficult. The above-mentioned process is executed by photolithography as shown in FIG. 1D, therefore the mask alignment of the photoresist 26 becomes difficult because the mark 26A is formed in the middle of the pad oxide film 24. Namely, the wafer must be once exposed, then coated with a photoresist, and then alignment is performed. Accordingly, the alignment becomes difficult. Further, because the alignment marks 23A and 26A are formed in the pad oxide film 24, which is in contact with a back surface of the wafer, a problem may arise. Namely, if the alignment mark 26A is formed in the middle of the pad oxide film 24, and if a foreign material attaches to the mark 26A in the middle of the wafer process, a minute defect occurs on the wafer surface because a foreign material such as silicon collides with the photoresist 26. This causes degradation of electrical characteristics such as an increase in electrical resistance. In the device isolation process using the photolithography, the mask alignment has been conventionally executed by using two alignment marks. However, as described above, the mask alignment of the photoresist becomes difficult because of forming the alignment marks on the same plane as the pad oxide film. Accordingly, the conventional device isolation process requires three alignment marks, i.e., the alignment marks 23A and 26A of the photoresist and the alignment mark 20A of the pad oxide film. Accordingly, it is possible to cause a problem in aligning the mask. Further, in the device isolation process, a number of semiconductor integrated circuits are simultaneously processed in the same mask, and accordingly, the alignment mark can be transferred to each of the wafer. However, as described above, the alignment mark is formed on the same plane as the pad oxide film, the wafer alignment of the mask becomes difficult because the mark 26A is formed in the middle of the pad oxide film 24. This results in an increase of rejects. Furthermore, the semiconductor integrated circuit which processes the large amount of data, for example DRAM requires a number of memory cells. In this case, the gate grooves for electrically connecting the memory cells to one another, and the device isolation grooves are formed. In this case, it is difficult to realize a high integration of the device because of the large width of the grooves. To solve this problem, the grooves must be formed in a minute pattern, and therefore it is necessary to deposit the film in a thickness of 200 nm or more on the above-mentioned process, which results in difficulty in the above-mentioned photolithography. FIG. 2A is a diagram showing a schematic of another conventional laser beam processing apparatus. FIG. 2B is a diagram showing an irradiation area on a semiconductor substrate. In the processing apparatus shown in FIG. 2A, a laser beam is irradiated on the semiconductor substrate 21 which is supported by a dicing saw 11. A semiconductor wafer 30 includes a silicon substrate 21 having a large number of semiconductor devices formed thereon. A plurality of device regions, for example 12, are formed by a device isolation process and a MOS transistor is formed in each of the device regions 12. A gate groove 10 is formed in an edge portion of the semiconductor wafer 30. The silicon substrate 21 is formed by stacking silicon dioxide, a pad oxide film, a silicon nitride film, a silicon dioxide film, and a silicon nitride film. A MOS transistor is formed in each of the device regions 12, and an element isolation groove 20A is formed in the same plane as the gate grooves 10. The dicing saw 11 is provided with a dicing tape 14 between the semiconductor substrate 21 and the dicing saw 11 to prevent disconnection of the silicon substrate 21. A groove dicing blade 13 forms the groove 10 by irradiating a laser beam 27 on the semiconductor substrate 21 on which the dicing tape 14 is coated. As shown in FIG. 2A, the semiconductor wafer 30